Number of items: 6.
Register bypassing in an asynchronous superscalar processor. (1999)
S.J. Davies,
C.J. Elston
and
P. Findlay
Hades - towards the design of an asynchronous superscalar processor. (1995)
C.J. Elston,
B. Christianson,
P. Findlay
and
G.B. Steven
HARP: a VLIW RISC processor. (1991)
P. Findlay,
S.A. Trainis,
G.B. Steven
and
R.G. Adams
The development of iHARP: a multiple instruction issue processor chip. (1991)
G.B. Steven,
R.G. Adams,
P. Findlay
and
S.A. Trainis
iHarp: a Multiple Instruction Issue Processor. (1992)
G.B. Steven,
R.G. Adams,
P. Findlay
and
S.A. Trainis
iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features. (1992)
S.A. Trainis,
P. Findlay,
G.B. Steven,
R.G. Adams
and
D. McHale
This list was generated on Wed Jul 22 02:35:54 2026 BST.